In electronic packaging, chips can be stacked in a three-dimensional configuration. A through silicon via (“TSV”) can be used for coupling two chips in the package. The TSV is formed of a conductive material that passes through the silicon wafer to electrically couple the chips. The conductive material, such as copper, has a different coefficient of thermal expansion (“CTE”) than the surrounding silicon. For example, the CTE of copper is approximately five times greater than the CTE of silicon. During a temperature cycle, the conductive material in the TSV can expand and contract. In effect, the conductive material can impose a force on the dielectric material that surrounds the TSV.
Over the course of one or more temperature cycles, the dielectric material can weaken and begin to crack. Connections between conductive materials can break causing open circuits to develop, or conductive materials separated by dielectric material can be damaged resulting in leakage. This breaking or cracking is particularly problematic with low-k dielectric materials. Low-k dielectric materials are often used for minimizing capacitance between the metal layers. However, low-k dielectric materials have weak mechanical strengths and are subject to breaking near the interface of the conductive material and the low-k dielectric material. As a result, there are reliability concerns with three-dimensional chip stacking in an electronic package. It also has been found that cracking is not always predictable and depends on the properties of the materials, feature sizes, and geometries used plus external factors such as mechanical stresses and temperature cycling. Therefore, it would be desirable to develop a sensor and method of use for detecting damage to the low-k dielectrics over the course of repeated thermal cycles before delamination occurs.